1. Field of the Invention
The present invention relates to a semiconductor device having a titanium-based metal wiring layer on an insulation film and, more particularly, to a semiconductor device having improved adhesion properties between the wiring layer and the insulation film and a method of manufacturing the same.
2. Description of the Related Art
In recent years, with the higher integration for integrated circuits, and demands for high-speed operations, suppression of wiring capacitance in an integrated circuit has become a serious problem. When the wiring interval is on an order of submicrons, the capacitance between interconnections abruptly increases to prolong the propagation delay of a signal. Particularly, in a high-speed logic circuit used for a CPU and the like, wiring on a chip is multi-layered. Extensive studies have been made for demanding an insulation film having a low dielectric constant suitable for an integrated circuit chip.
As a conventional insulation film for an integrated circuit, a silicon oxide film (SiO.sub.2) is widely used. The dielectric constant of a silicon oxide film formed by general CVD is about 4.2 to 5.0. To decrease this dielectric constant to substantially half, an organic polymer (a dielectric constant of 2.0 to 3.1) is known. The organic polymer, however, has problems of insufficient thermal stability and difficult patterning.
Recently, it is examined to form an insulation film (a dielectric constant of 3.0 to 3.6) containing Si-F bonds by adding fluorine (F) into a silicon oxide film and to decrease the dielectric constant of the insulation film. An insulation film containing Si-F bonds is a material which receives attention for its excellent burying properties in a multi-layered interconnection. By trapping fluorine into an oxide film, an insulation film having a low dielectric constant can be realized. This is reported in, e.g., "Reduction of Wiring Capacitance with New Low Dielectric SiOF Interlayer Film for High Speed/Low Power Sub-half Micron CMOS" (J. Ida et al., 1994 Symposium on VLSI (p. 59)). This reports that the propagation delay time (tpd) of a 0.35-fm CMOS 2NAND gate was improved 13% in an interconnection with an insulation film (a dielectric constant of 3.6) containing Si-F bonds in comparison with an interconnection with a normal CVD oxide film (a dielectric constant of 4.3).
In this manner, an insulation film containing Si-F bonds has a low dielectric constant and an effect of decreasing wiring capacitance. On the other hand, this insulation film has a drawback of insufficient adhesion properties with a refractory metal wiring layer to cause peel-off of the wiring layer. The situation will be described with reference to the accompanying drawing.
FIG. 1 is a partial sectional view showing a semiconductor device having a two-layered interconnection formed on its surface. More specifically, a semiconductor element (not shown) is formed on the surface of a silicon substrate 111, and its entire upper surface is covered with a first insulation film 112 consisting of silicon oxide. A wiring underlayer 113a consisting of titanium (Ti) is formed on the surface of the first insulation film 112. A main wiring layer 113b made of Cu, Al-Si-Cu, or the like is stacked on the wiring underlayer 113a, and these stacked layers form a first metal interconnection 113. By adopting the two-layered structure in this manner, the mechanical strength with respect to disconnection and the like can be enhanced without increasing the electrical resistance of an interlayer. This first wiring layer is connected to the semiconductor element (not shown) formed on the substrate 111 through a via conductor (not shown).
A second insulation film 115 of silicon dioxide (SiO.sub.2) containing Si-F bonds is formed on the entire surface of the first metal interconnection 113. Via holes are partially formed on the first metal interconnection 113, and plugs 116 made of tungsten (W) are buried in these via holes. A second wiring underlayer 117a of titanium (Ti) and a second main wiring layer 117b of Cu, Al-Si-Cu, or the like are stacked on this second insulation film 115 to form a second metal interconnection 117. A third insulation film 119 consisting of silicon dioxide (SiO.sub.2) is formed on this structure.
In the semiconductor device manufactured in this manner, the second metal interconnection 117 on the surface may peel off from the second insulation layer 115 due to a residual thermal stress generated in the wiring layer and a mechanical impact during bonding. It is considered that this peel-off is caused by poor adhesion properties between the insulation layer 115 containing Si-F bonds and the titanium wiring underlayer 117a.
As described above, in the semiconductor device having an insulation film containing Si-F bonds and a titanium wiring layer, the adhesion properties at the interface between the titanium wiring layer and the insulation film are degraded. Consequently, the metal wiring film is caused to peel off due to a thermal stress generated in the metal wiring film and a mechanical stress during bonding.